Embodiments of the present invention generally relate to integrated circuits and the processing for the manufacture of semiconductor devices. More particularly, embodiments of the invention provide a method and device for monitoring charging effects in the manufacture of integrated circuits. Merely by way of example, the invention has been applied to reducing and monitoring electrical charges on processed and/or partially processed integrated circuits. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is chemical dry etching process used for the manufacture of integrated circuits in a cost effective and efficient way.
The manufacturing of integrated circuits involves various processes. For example, the processes include, among others, wafer growth, photolithography, doping, oxidation, deposition, etching removal, and epitaxial growth.
Semiconductor devices and circuits are formed in wafers, which serve as substrates. Generally, single-crystal substrates, which are made from a single material with crystals formed by atoms all aligned in a specific direction. The process of waver creation usually involves creating a large ingot of semiconductor materials, aligning the ingot, removing impurities, slicing ingot into thin wafers, and polishing the sliced wafers.
Generally, photolithography processes are used to define and shape specific areas of the wafer to suit particular design of an integrated circuit. Usually, a layout design is used to create an optical mask (or reticle). The wafer surface is usually covered with a layer of photoresist. The wafer is then exposed to light through the optical mask. After light exposure, the areas of photoresist that were exposed to light are removed using chemical process. As a result, the wafer contains both clear areas (where photoresist is removed) and areas blocked by photoresist. Next, various processes (such as etching, oxidation, diffusion, etc.) only affecting clear areas are performed. After various processes are finished, photoresist materials are then removed.
One of the various processes is oxidation, which creates insulating layers. Often, oxide grows on silicon in a wafer to form dielectrics made of SiO2. One of the method to grow oxide on wafer is exposing wafer to O2 at high temperatures.
Deposition is another process in the semiconductor fabrication. Deposition provides connections among insulators and interconnecting layers by depositing various materials. Techniques such as chemical vapor deposition (CVD) and lower pressure CVD (LPCVD) are commonly used. For example, metals are deposited to provide low resistance interconnects, polysilicon is used as conductor, and dielectric materials and/or field oxide are deposited to create insulating layers.
Another processes is doping, which changes the electrical properties of the wafer. For example, a specific area of the wafer may be doped and become n-type or p-type depending upon the doping material used and its concentration. There are several ways to perform doping. One way is implantation, in which atoms are injected into wafers at high velocity. Another way of doping is through diffusion, in which atoms are diffused into selected region of the wafer at high temperature.
Etching is another important process in the semiconductor fabrication. Etching involves removing selected regions from the surface of a wafer using physical process, chemical process, or the combination thereof. Usually the objective of etching is to faithfully reproduce masking patterns. To achieve this objective, it is often desirable for the etching process to be highly selective both in patterns and depth, which is often achieved through chemical dry etching.
Chemical dry etching usually involves generating reactive species in a plasma, diffusing these species to the surface of material being etched, species being absorbed, reacting these species on the surface to form volatile by-products, desorbing the by-products from the surface, and diffusing the desorbed species into gas. There are many various dry-etch systems to accomplish these steps. For example, dry-etch systems include barrel etchers, downstream etchers, parallel-electrode (planar) reactor etchers, stacked parallel-electrode etchers, hexode batch etchers, magnetron ion etchers, etc.
Typically, an integrated circuit fabrication goes through the abovementioned processes multiple times. During these processes, electrical charges build up on the wafer surface. For example, processes such as plasma etching, ashing, ion implantation all can cause electrical charge build up. Often, electrical charge build up leads to wafer unreliability and other problems.
As transistor sizes continue to decrease, the gate oxide becomes increasingly more susceptible to process induced damage. When plasma is used in various fabrication steps, localized build up creates significant electric fields that produce tunneling current. Defects initiated by this tunneling current cause decreased breakdown voltages, increased leakage current, and deteriorated oxide reliability.
Plasma is needed in MOSFET processing for many fabrication steps such as sputtering, etching, photoresist ashing, and dielectric deposition. Exposure to plasma may result in damage from unwanted oxide charging.
One of the conventional techniques for monitoring electrical charges is to use special test wafers. FIG. 1 is a simplified diagram illustrating a conventional test structure for monitoring wafer charges. As shown in FIG. 1, a test structure 100 includes an EEPROM cell 102 and an antenna 101. The antenna 101 is connected to the EEPROM cell 102 and collects charges thereof.
The test structure 100 of the prior art can be an effective tool for certain applications. However, the test structure 100 is a specific test structure that requires an expensive fabrication process and that may not be used for every integrated circuit that is manufactured. As a result, the application of the test structure 100 is often limited to equipment diagnosis and calibration.
Another prior art technique for monitoring and partially removing electrical charges uses an area-intensive conductor relatively to terminals of metal-oxide semiconductors. FIG. 2 is a simplified diagram illustrating a conventional test structure for measuring electrical charges on semiconductors. As shown in FIG. 2, the test structure 200 includes an antenna 201 that is connected to a gate 203 of a MOSFET 202. For example, the antenna 201 has a large area that is connected to the floating gate 203. The antenna 201 collects electrical charges (i.e., leakage at the gate oxide) from the gate 203. By measuring the electrical charges, the charging effects due to various processes can be evaluated. Typically, the test structure 200 can be implemented as full flow electrical structures manufactured together with real products, under the assumption that the test structure 200 will likely mirror the electrical charges on real products.
Therefore, an improved system and method for reducing and monitoring electrical charging on wafers is desired.